Analog Devices Inc. AD9988 4T4R Direct RF Receiver & Transmitter

Analog Devices Inc. AD9988 4T4R Direct RF Receiver and Transmitter is a highly integrated device with four 16-bit, 12GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The AD9988 supports four transmitter channels and four-receiver channels with a 4T4R configuration.

The ADI AD9988 4T4R Direct RF Receiver and Transmitter is designed for four-antenna TDD transmitter applications, where the receiver path is shared between receiver and observation modes. Phase coherency is maintained while the GPIO pins can be configured and toggled to support different user modes. The device offers a maximum radio channel bandwidth of 1.2GHz in a 4T4R configuration and a sample resolution of 16 bits.

The AD9988 features a 16-lane 24.75Gbps JESD204C or 15.5Gbps JESD204B serial data port that allows up to eight lanes per transmit/receive link, an on-chip clock multiplier, and digital signal processing capability targeted at multiband direct to RF radio applications.

Features

Flexible, reconfigurable radio common platform design
- Transmitter/receiver channel bandwidth up to 1.2GHz (4T4R)
- RF DAC/RF ADC RF frequency range up to 7.5GHz
- On-chip PLL with multichip synchronization
  - External RF clock input option
Versatile digital features
- Selectable interpolation and decimation filters
- Configurable DDCs and DUCs
  - 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC)
  - 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC)
  - FDUCs and FDDCs are fully bypassable
  - 2 independent 48-bit NCOs per DUC or DDC
- Programmable 192-tap PFIR filter for receive equalization
  - Supports 4 different profile settings loaded via GPIO
- Receive AGC support
  - Fast detect with low latency for fast AGC control
  - Signal monitor for slow AGC control
  - Dedicated AGC support pins
- Transmit DPD support
  - Programmable delay and gain per transmit data path
  - Coarse DDC delay adjust for DPD observation path
- Supports real or complex digital data (8-, 12-, or 16-bit)

Auxiliary features
- ADC clock driver with selectable divide ratios
- Power amplifier downstream protection circuitry
- On-chip temperature monitoring unit
- Programmable GPIO pins support toggling between modes
- TDD power savings option and sharing ADCs
SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75Gbps
- 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx)
- Supports Subclass 1
Supports multidevice synchronization
15mm x 15mm, 324-ball BGA with 0.8mm pitch