Altera / Intel SoC FPGA Family

Intel SoC FPGAs integrate an Arm-based hard processor system (HPS) consisting of processors, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. They combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable Arm-based SoC FPGAs are ideal for reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA. They differentiate the end product with custom hardware and software and add support for virtually any interface standard or protocol in the FPGA.

Intel SoC FPGAs extend product life and revenue through hardware and software updates in the field. They also improve system performance via a high-bandwidth interconnect between the processor and the FPGA. These devices join the diverse family of Cyclone® V and Arria® V FPGAs with dozens of devices and variations and include additional hard logic such as PCI Express® Gen2, multiport memory controllers, and high-speed serial transceivers. Built on TSMC's 28nm Low-Power (28LP) process, the SoC FPGAs drive down power and cost while enabling performance levels required by cost-sensitive applications.


  • Processor Architecture
    • Dual-core Arm Cortex-A9 MP core processor
      • Up to 800MHz maximum frequency
      • Support for symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP)
    • Each processor core includes:
      • 32KB of L1 instruction cache
      • 32KB of L1 data cache
      • NEON media processing engine
      • Single- or double-precision floating-point unit
      • Memory management unit (MMU)
      • Private interval timer
      • Private watchdog timer
      • 512KB of shared level 2 (L2) cache
    • SCU for cache coherency
    • Accelerator coherency port (ACP)
    • Global timer
    • Generic interrupt controller
    • CoreSight™ instruction trace
  • Memory Interface Support
    • Multiport SDRAM controller subsystem
      • DDR2 and DDR3
      • LPDDR1 and LPDDR2
      • Error correction code (ECC)
    • Flash memory controller
      • NAND with direct memory access (DMA) and optional ECC
      • Quad SPI (NOR)
      • Secure Digital (SD)/ secure digital I/O
      • (SDIO)/ MultiMediaCard (MMC) with DMA
  • Interface Peripherals
    • Two 10/100/1000Mbps Ethernet media access controllers (EMACs) with DMA
    • Two USB 2.0 On-The-Go (USB OTG) controllers with DMA
    • Four I²C controllers
    • Two controller area networks (CAN), two master SPIs, two slave SPIs, UART
    • Up to 71 general-purpose I/Os (GPIOs) and 14 input-only
  • On-Chip Memory
    • 64KB on-chip RAM
    • 64KB on-chip boot ROM
  • Debug
    • IEEE standard 1149.1-2001 (JTAG)
      • CPU Debug Access Port (DAP)
      • Direct memory debug via Advanced High-performance Bus Access Port (AHB-AP)
    • Embedded trace router (ETR) port with DMA
      • Processor trace
      • System bus trace
      • Operating system (OS) trace
    • On-chip trace storage
  • System Peripherals
    • Four general-purpose timers
    • Two watchdog timers
    • 8-channel DMA controller
    • FPGA manager for FPGA configuration
    • Clock and reset managers
  • HPS/FPGA Interfaces
    • HPS-to-FPGA bridges
      • Processor and DMA access to FPGA peripherals
      • Configurable 32-, 64-, or 128-bit Advanced Microcontroller Bus Architecture (AMBA®) Advanced eXtensible Interface (AXI™)
    • FPGA-to-HPS bridges
      • FPGA masters access processor subsystem peripherals
      • Configurable 32-, 64-, or 128-bit AMBA AXI interface
      • Coherent access to processor cache through ACP
      • FPGA-to-HPS SDRAM controller subsystem interface
      • FPGA access to DRAM for shared memory
      • Up to 6 masters, 4x 64-bit read, 4x 64-bit write data
    • Miscellaneous
      • FPGA-to-HPS interrupts
      • DMA handshake (allows FPGA peripherals to perform block-level transfers with system DMA controller)
      • More than 100Gbps HPS-to-FPGA and FPGA-to-HPS bandwidth

Cyclone V System Level Cost Savings Through Integration

Chart - Altera / Intel SoC FPGA Family

Reducing Total System Cost Through Integration

Because Cyclone V integrates an abundance of hard intellectual property (IP) blocks, the user can differentiate and do more with less overall system cost, power, and design time. Key hard IP blocks include the following:

• Hard memory controllers supporting 400MHz DDR3 SDRAM with optional error correction code (ECC) support
• PCI Express® (PCIe®) Gen2 with multifunction support
• Variable-precision digital signal processing (DSP) blocks
• HPS Dual-core ARM Cortex-A9 MPCore processor

Gepubliceerd op: 2012-11-19 | Bijgewerkt op: 2023-03-31