The AVR core of the ATmega128RFR2 Wireless Module combines a rich instruction set with 32 general-purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Two independent registers can be accessed with one single instruction executed in one clock cycle. The resulting architecture is very code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The system includes internal voltage regulation and advanced power management. Distinguished by the small leakage current, it allows an extended operation time from battery.
The radio transceiver is a fully integrated ZigBee solution using a minimum number of external components. It combines excellent RF performance with low cost, small size, and low current consumption. The radio transceiver includes a crystal-stabilized fractional-N synthesizer, transmitter and receiver, and full Direct Sequence Spread Spectrum Signal (DSSS) processing with spreading and despreading. The ATmega128RFR2 is fully compatible with IEEE802.15.4-2011/2006/2003 and ZigBee standards.
The ATmega128RFR2 features 128K Bytes of In-System Programmable (ISP) Flash with read-while-write capabilities, 4K Bytes EEPROM, and 16K Bytes SRAM. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the AVR core.
Atmel / Microchip ATmega128RFR2 Wireless Module is offered in a 64-pad QFN (Quad Flat No-lead) RoHS-compliant package.