Microchip Technology PIC32CZ CA70/MC70 Microcontrollers

Microchip Technology PIC32CZ CA70/MC70 Microcontrollers are based on the high-performance 32-bit Arm^® Cortex^®-M7 processor with a Double Precision Floating Point Unit (FPU). The MCUs operate at up to 300MHz and supplement up to 2048Kbytes of Flash and up to 512Kbytes of multi-port SRAM, which are configurable instruction and data tightly coupled memories that leverage the core's advanced DSP capabilities.

The Microchip PIC32CZ CA70/MC70 Microcontrollers contain a 10/100 Ethernet MAC w/IEEE1588, an HS USB Interface with integrated PHY, dual CAN-FD, QSPI, CMOS Imager interface, MediaLB, TDM/I²S (SSC), multiple serial interfaces, and onboard hardware cryptography, including TRNG, AES-256, and SHA-256 engines.

Supported by MPLAB^® X IDE and MPLAB Harmony.

Features

Operating Conditions
- 2.5V to 3.6V, -40°C to +85°C, DC to 300MHz
- 2.5V to 3.6V, -40°C to +105°C, DC to 300MHz
AEC - Q100 Grade 2 (-40°C to +105°C) qualification
Core
- Arm Cortex-M7 running at up to 300MHz
- 16KB of I-Cache and 16KB of D-Cache with Error Code Correction (ECC)
- Single-precision and double-precision HW Floating Point Unit (FPU)
- Memory Protection Unit (MPU) with 16 zones
- DSP Instructions, Thumb^®-2 Instruction Set
- Embedded Trace Module (ETM) with instruction trace stream, including Trace Port Interface Unit (TPIU)
Memories
- 2048KB embedded Flash with unique identifier and user signature for user-defined data
- Up to 512KB embedded Multi-port SRAM
- Up to 256KB Tightly Coupled Memory (TCM)
- 16KB ROM with In-Application Programming (IAP) routines
- One External Bus Interface (EBI) (optional) containing a 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD module, NOR, and NAND Flash with on-the-fly scrambling
Cryptography
- True Random Number Generator (TRNG)
- AES: 256-bit, 192-bit, 128-bit key algorithm, compliant with FIPS PUB-197 specifications
- Integrity Check Monitor (ICM) supports Secure Hash Algorithm SHA1, SHA224, and SHA256
System
- Embedded voltage regulator for single-supply operation
- Power-on-Reset (POR), Brown-out Detector (BOD), and dual watchdog for safe operation
- RTC with Gregorian calendar mode, waveform generation in low-power modes
- RTC counter calibration circuitry compensates for 32.768kHz crystal frequency variations
- 32-bit low-power Real-Time Timer (RTT)
- Temperature sensor
- One dual-port 24-channel central DMA Controller (XDMAC)
Power management of single or dual power supply capability
Clock management
- Quartz or ceramic resonator oscillators at 3MHz to 20MHz main oscillator with failure detection, 12MHz or 16MHz needed for USB operations, optional low-power 32.768kHz for RTC or device clock
- High-precision Main RC oscillator with 12MHz default frequency
- 32.768kHz crystal oscillator or Slow RC oscillator as a source of low-power mode device clock (SLOW_CLK)
- One 500MHz PLL for system clock
- One 480MHz PLL for USB high-speed operations
Low-power features
- Low-power sleep, wait, and backup modes, with typical power consumption down to 1.1μA in Backup mode with RTC, RTT, and wakeup logic enabled
- Ultra-low-power RTC and RTT
- 1KB of backup RAM (BRAM) with a dedicated regulator

Communication interfaces
- One (optional) Ethernet MAC (GMAC)
  - 10/100Mbps in MII and RMII with dedicated DMA
  - IEEE^® 1588 PTP frames support
  - IEEE 802.1AS Timestamping support
  - IEEE 802.1Qav credit-based traffic shaping hardware support
  - 802.3az energy-efficient support
  - Ethernet AVB support
- USB 2.0 Device/Mini Host High-speed (USBHS) at 480Mbps, 4KB FIFO, up to 10 bidirectional endpoints, dedicated DMA
- 12-bit ITU-R BT. 601/656 Image Sensor Interface (ISI)
- Up to two host Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD) with SRAM-based mailboxes, time-triggered and event-triggered transmission
- MediaLB® device (optional) with 3-wire mode, up to 1024 x Fs speed, supporting MOST25 and MOST50 networks
- Up to three USART with LIN, ISO7816, IrDA^®, RS-485, SPI, Manchester, Modem and LON (USART1 only) modes support
- Up to five 2-wire UARTs with SleepWalking™ support
- Up to three Two-Wire Interfaces (TWIHS) (I²C-compatible) with SleepWalking support
- Quad I/O Serial Peripheral Interface (QSPI) interfacing up to 256MB Flash and with eXecute-in-place and on-the-fly scrambling
- Up to two Serial Peripheral Interfaces (SPI)
- One Serial Synchronous Controller (SSC) with I²S and TDM support
- Up to two Inter-IC Sound Controllers (I²SC)
- One High-speed Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC) (optional)
Timers/output compare/input capture
- Four 3-channel 16-bit Timer/Counters (TC) with Capture, Waveform, Compare, and PWM modes, constant on time, quadrature decoder logic, and 2-bit gray up/down counter for stepper motor
- Two 4-channel 16-bit PWMs with complementary outputs, Dead Time Generator and eight fault inputs per PWM for motor control, two external triggers to manage power factor correction (PFC), DC-DC, and lighting control
Advanced analog and touch
- Two Analog Front-End Controllers (AFEC), each supporting up to 24 channels with differential input mode and programmable gain stage, allowing dual sample-and-hold (S&H) at up to 1.7Msps, with offset and gain error correction feature
- One 12-bit, up to 2-channel, 1Msps-per-channel Digital-to-Analog Controller (DAC) with differential and over-sampling modes
- One Analog Comparator Controller (ACC) with flexible input selection, selectable input hysteresis
I/O
- Up to 114 I/O lines with external interrupt capability (edge- or level-sensitivity), debouncing, glitch filtering, and on-die series resistor termination
- Five Parallel Input/Output Controllers (PIO)