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Terasic Video Development Systems for Altera Cyclone® V

Terasic Video Development Systems for Altera Cyclone® V

Terasic Video Development Systems for Altera Cyclone® V are ideal video processing platforms for high-performance, cost-effective video applications.

The Cyclone V E Development Kit offers multiple banks of DDR3 and LPDDR2 memory, providing the ideal low-cost platform for high-bandwidth video processing. Additional features include an LCD character display, LEDs, user switches, USB and RJ-45 connectors.

The Cyclone V GX kit features PCIe x4 lanes and high-speed 3.125Gbps transceiver capabilities, allowing for a myriad of functionalities such as prototyping, power measurement, and high-speed communication. Memory interfaces include flash memory, SRAM, and DDR3, creating a complete integrated memory interface solution for memory-intensive applications.

Each Video Development System includes a DVI-HSMC daughter card as part of the bundled package, which will allow developers to access high quality and high resolution video signals that can support resolution up to 1600x1200. A complete DVI video controller design with source code is provided.

These platforms can also allow users to experience advanced image processing designs incorporating VIP (Altera's Video and Image Processing Suite MegaCore Functions).

VDS for Altera Cyclone V E Features
  • Cyclone V E FPGA - 5CEFA7F31C7NES
  • MAX V CPLD - 5M2210ZF256I5N (system controller)
  • MAX II CPLD - EPM240M100I5N (embedded USB Blaster II)
  • On-board USB-Blaster™ II cable (USB, PHY, Max® V CPLD)
  • JTAG direct via JTAG header
  • Memory: DDR3 x32 at 300MHz (soft memory controller), LPDDR2 x16 (soft memory controller), Flash (512Mb), SSRAM (18Mb), EEPROM (64Kb)
  • LCD: Character LCD (16x2)
  • Components and interfaces: RJ45 for Ethernet,
    UART interface
  • Quartus® II design software information: Quartus II Web Edition Software

Terasic DVI-HSMC Card Features
  • Digital Transmitter
    • One DVI transmitter with single transmitting port
    • Digital Visual Interface (DVI) compliant
    • Supports resolutions from VGA to UXGA (25 – 165MHz pixel rates)
    • Universal Graphics Controller Interface
      • 12-Bit, Dual-Edge and 24-Bit, Single-Edge input modes
      • Adjustable 1.1 to 1.8V and standard 3.3V CMOS input signal levels
      • Fully Differential and Single-Ended Input clocking modes
      • Standard Intel 12-Bit Digital Video Port compatible as on Intel™ 81x chipsets
    • Enhanced PLL Noise Immunity: On-chip regulators and bypass capacitors for reducing system costs
    • Enhanced Jitter Performance
      • No HSYNC jitter anomaly
      • Negligible data-dependent jitter
        • Programmable using I²C serial interface
        • Single 3.3V supply operation
  • Digital Receiver
    • One DVI receiver with single receiving port
    • Supports UXGA resolution (output pixel rates up to 165MHz)
    • Digital Visual Interface (DVI) specification compliant
    • True-color, 24bit/pixel, 16.7M colors at 1 or 2-pixels per clock
    • Laser trimmed internal termination resistors for optimum fixed impedance matching
    • 4x over-sampling
    • Reduced ground bounce using time staggered pixel outputs
    • Lowest noise and best power dissipation using TI PowerPAD™ packaging

VDS for Altera Cyclone V GX Features
  • Cyclone V GX FPGA - 5CGXFC7D6F31C7NES
  • MAX ® V CPLD - 5M2210ZF256C4N (system controller)
  • MAX II CPLD - EPM240M100C4N (embedded
    USB-Blaster™ II)
  • MAX II CPLD- EPM240M100C4N (optional, third party security CPLD feature)
  • Embedded USB-Blaster II (JTAG)
  • Fast Passive Parallel (PFL)
  • Push buttons, DIP switches and LEDs
  • Memory: Two banks x40 bit DDR3 SDRAM with error correction code (ECC), 512Mb flash memory and
    18MB SRAM
  • Standard communication ports: USB 2.0, Gigabit Ethernet, PCIe x4 Edge Connector, universal high-speed mezzanine card (HSMC) (x4 Xvcrs, x16 Tx LDVS, x16 Rx LVDS), one serial digital interface (SDI) channel, two SMAs for one transceiver channel
  • Clocking:
    • Programmable clock generator for FPGA reference clock input
    • 125MHz LVDS oscillator for FPGA reference clock input
    • 148.5/148.35MHz LVDS VCXO for FPGA reference clock input
    • 50MHz single-ended oscillator for FPGA and MAX V FPGA clock input
    • 100MHz single-ended oscillator for MAX V FPGA configuration clock input
    • SMA input (LVPECL)

Altera Cyclone® V FPGAs

Altera Cyclone® V 28nm FPGAs provide the industry's lowest system cost and power, along with performance levels that make the device family ideal for differentiating your high-volume applications. Users will get up to 40% lower total power compared with the previous generation, efficient logic integration capabilities, integrated transceiver variants, and SoC FPGA variants with an ARM-based hard processor system (HPS). The family comes in six targeted variants.
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VDS for Altera Cyclone V E Board Layout

Video Dev System for Altera Cyclone V E Board Layout (click for full view)
VDS for Altera Cyclone V GX Board Layout

Video Dev System for Altera Cyclone V GX Board Layout (click for full view)
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  • Terasic Technologies
  • Development Tools|Embedded Solutions
Gepubliceerd op: 0001-01-01 | Bijgewerkt op: 0001-01-01