Texas Instruments CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers
Texas Instruments CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers have two serial inputs (A and B) connected through an AND gate and an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data line high; a low signal on either will set the input data line low. Data at A and B can be changed while CLK is high or low, provided the minimum set-up time requirements are met.
The CLK pin of the Texas Instruments CD74AC164/CD74ACT164 is rising-edge triggered, activating the transition from LOW to HIGH. Upon a positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The data of the last register, QH, will be discarded at each clock trigger. If a low signal is applied to the CLR pin, then the CD74AC164/CD74ACT164 will immediately set all registers to a logical low value.
Features
- Buffered inputs
- Typical propagation delay of 6ns at VCC = 5V, TA = 25°C, CL = 50pF
- SCR-latch-up-resistant CMOS process and circuit design
- Speed of bipolar FAST™/AS/S with significantly reduced power consumption
- Balanced propagation delays
- AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply
- ±24mA output drive current
- Fanout to 15 FAST™ ICs
- Drives 50Ω transmission lines
Fuctional Block Diagram
Related Development Tool
Texas Instruments 14-24-LOGIC-EVM Logic Evaluation Module (EVM)
Generic evaluation module developed to support any TI logic leaded device in a 14 to 24 pin count.
Published: 2024-12-04
| Updated: 2024-12-12